[doc] AON Timer wdog bite reset missing sw initialization documentation

### Description

To enable the AON Timer watchdog bite reset functionality, it seems that some additional configuration is needed to be performed by SW in the pwrmgr. The steps were found from the AON timer bark/bite test:
1. Write 1 to the watchdog reset bit in pwrmgr.[RESET_EN](https://opentitan.org/book/hw/top_earlgrey/ip/pwrmgr/data/autogen/pwrmgr.html#reset_en) (looking at the test for earlgrey, it uses bit 1)
2. Write 1 to the pwrmgr.[CFG_CDC_SYNC](https://opentitan.org/book/hw/top_earlgrey/ip/pwrmgr/data/autogen/pwrmgr.html#cfg_cdc_sync) register
3. Poll the pwrmgr.CFG_CDC_SYNC until reading 0.

These steps are not documented in the watchdog programmer's guide, nor are they documented in the pwrmgr. Unless I am missing something, without this configuration sequence the watchdog bite will not reset the system even when enabled. Please make a note of this in the AON timer documentation.

Issue was tested on Verilator simulation.

Start with the AON timer watchdog programmer's guide and pwrmgr documentation, then compare them with the AON timer bark/bite test. Document the RESET_EN and CFG_CDC_SYNC writes and polling sequence; done when the required bite-reset initialization is explicit in the AON timer documentation.

Written by the indexing model from the issue text.