[dv,sw] CPU clock frequency in Verilator

For Verilator, the CPU (Ibex) clock frequency is currently defined as 500 kHz:
https://github.com/lowRISC/opentitan/blob/062a9b0bc67137315844a729b93e16d2afc33d37/sw/device/lib/arch/device_sim_verilator.c?plain=1#L20-L21

It is inherently difficult to define a meaningful frequency value in simulation as there is no correspondence to any wall-clock time or frequency (in contrast to emulation on FPGA or implementation on an IC). However, 500 kHz differs by 200x from how the CPU clock frequency is defined for DV simulations (100 MHz):
https://github.com/lowRISC/opentitan/blob/062a9b0bc67137315844a729b93e16d2afc33d37/sw/device/lib/arch/device_sim_dv.c?plain=1#L18-L20

The problem is that any CPU timeout functions, which take a _time_ as argument (e.g., microseconds), are relative to those frequency definitions. In consequence, a timeout that is reasonable for DV simulations is much too restrictive for Verilator simulations, and a timeout that is reasonable for Verilator simulations is much too lax for DV simulations. See [this example](https://github.com/lowRISC/opentitan/blob/062a9b0bc67137315844a729b93e16d2afc33d37/sw/device/tests/rv_core_ibex_rnd_test.c#L29-L35) where a timeout of 12.5 ms would suffice for DV simulation but 2.5 s is required for Verilator.

Can't we use the same CPU clock frequency value in Verilator as in DV simulations?

Compare the CPU frequency definitions in sw/device/lib/arch/device_sim_verilator.c and device_sim_dv.c, then inspect the timeout usage in sw/device/tests/rv_core_ibex_rnd_test.c. Verify that using the same frequency gives consistent timeout behavior in both Verilator and DV simulations.

Written by the indexing model from the issue text.