lowRISC / lowRISC/opentitan

[rv_core_ibex/top, rtl] Regularise use of timer interrupt

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Earlgrey-PROD Candidate IP:rv_core_ibex Type:FutureRelease
Dominant language
SystemVerilog
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Description

The timer interrupt from rv_timer is directly wired into rv_core_ibex where it requires synchronisation. It would be preferable to route this via the PLIC as with other interrupts and deal with the synchronisation there.

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First steps

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  3. Fork the repository and make your change on a branch.
  4. Open a pull request that references the issue number.

Research direction

Start in the RTL integration named in the title, tracing the timer interrupt from rv_timer into rv_core_ibex and comparing that path with other interrupts through the PLIC. Confirm where synchronization is currently required, then verify that the timer follows the PLIC path and the direct connection is removed.

Written by the indexing model from the issue text.

Assessment

Domain
embedded-iot
Issue type
Refactor
Difficulty
4/5
Estimated time
3-5 days
Activity status
Stale
Clarity
Mostly clear
Newbie friendliness
35/100

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