[test-triage] chip_sw_rv_core_ibex_lockstep_glitch

### Hierarchy of regression failure

Block level

### Failure Description

```
Offending 'pend_req[d2h.d_source].pend'
UVM_ERROR @ 1979.151724 us: (tlul_assert.sv:256) [ASSERT FAILED] respMustHaveReq_M
UVM_INFO @ 1979.151724 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
```

### Steps to Reproduce

- GitHub Revision: [24fcee5a4](https://github.com/lowrisc/opentitan/tree/24fcee5a423290416785a58ca3de6328646c1bc9)
- dvsim invocation command to reproduce the failure, inclusive of build and run seeds:
```
./util/dvsim/dvsim.py hw/top_earlgrey/dv/chip_sim_cfg.hjson -i chip_sw_rv_core_ibex_lockstep_glitch --build-seed 4127990797 --fixed-seed 2215445585 --waves fsdb
```

### Tests with similar or related failures

- [ ] chip_sw_rv_core_ibex_lockstep_glitch