[dvsim] Riviera/Questa support is broken - around otbn_memutil

### Description

While trying to run dvsim with Riviera, I get:
```log
util/dvsim/dvsim.py hw/top_earlgrey/dv/chip_sim_cfg.hjson --tool=riviera
INFO: [dvsim] [proj_root]: /home/srini/proj/OpenTitan_Git/ot_rpro/opentitan
INFO: [SimCfg] [scratch_path]: [chip] [/home/srini/proj/OpenTitan_Git/ot_rpro/opentitan/scratch/master/chip_earlgrey_asic-sim-riviera]
ERROR: [SimCfg] Mode "riviera_otbn_memutil_build_opts" enabled on the command line is not defined
```

I see that the file: hw/ip/otbn/dv/memutil/otbn_memutil_sim_opts.hjson contains support for VCS, XLM, DSIM as

```hjson
build_modes: [
{
name: vcs_otbn_memutil_build_opts
build_opts: ["-CFLAGS -I{build_dir}/src/{otbn_memutil_src_dir}"]
}

{
name: xcelium_otbn_memutil_build_opts
build_opts: ["-I{build_dir}/src/{otbn_memutil_src_dir}"]
}

{
name: dsim_otbn_memutil_build_opts
build_opts: ["-c-opts -I{build_dir}/src/{otbn_memutil_src_dir}"]
}
]

```
But Riviera/Questa and maybe others are missing. I can attempt a fix if this is not often tested by OT team.

Thanks

Start with hw/ip/otbn/dv/memutil/otbn_memutil_sim_opts.hjson and the util/dvsim/dvsim.py command shown in the report. Compare the existing VCS, Xcelium, and DSim modes to determine the required Riviera and Questa support, then rerun the Riviera command; done means the requested mode is recognized instead of producing an undefined-mode error.

Written by the indexing model from the issue text.