[dv] Common warnings from VCS
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- SystemVerilog
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Description
### Description
Three common warnings from VCS when turn on coverage:
- [ ] Warning-[VCM-HFUFR] Hier Config: regions not found (compile time warning)
- [ ] Note-[VCM-NODRCO] Cannot analyze signal for constants (compile time warning)
- [ ] Warning-[FCIAVW] Invalid attribute value (runtime warning)
More explanations:
1). Warning-[VCM-HFUFR] Hier Config: regions not found
In `vcs/cover.cfg` we exclude common modules because they are individually pre-verified by other benches.
This error happens when the excluded modules are not instantiated in this specific design.
2). Cannot analyze signal for constants
For coverage collection, VCS seems to have issue when some ports are tied to constant. This error does not affect other functional check.
3). Warning-[FCIAVW] Invalid attribute value
https://cs.opensource.google/opentitan/opentitan/+/master:hw/dv/sv/sec_cm/prim_onehot_check_if.sv;l=63?q=PRIM_ONEHOT_CHECK_IF&ss=opentitan%2Fopentitan
If the `at_least` is set to 0, it means we expect 0 hits, but VCS will throw a warning for that.
**They are all DV enhancement, so I think we can waive this warnings for M2.5 signoff.**
CC: @jdonjdon @gdessouky @ballifatih @andreaskurth @vogelpi @GregAC @marnovandermaas @crteja
Contributor guide
Research direction
Review vcs/cover.cfg and the referenced prim_onehot_check_if.sv line to understand how the three VCS coverage warnings arise. Check the affected DV coverage flow first, then document or apply the warning waivers; done means the warnings are waived for M2.5 signoff without affecting functional checks.
Written by the indexing model from the issue text.
Assessment
- Domain
- testing-qa
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 30/100