[doc] Chip Level Testing Strategy
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- SystemVerilog
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Description
I would like to know if there is a system level programmer guide in top_earlgrey. Like pseudo code block operation description in [AES ip](https://opentitan.org/book/hw/ip/aes/doc/programmers_guide.html#block-operation) is a very good example for test understanding. I know OT has some DV test in [env folder](https://github.com/lowRISC/opentitan/tree/master/hw/top_earlgrey/dv/env/seq_lib), but it is still unclear how those connections between modules are made and how to program the system in order to test IP modules interaction or even RoT functionality like the spec in [top_earlgrey](https://opentitan.org/book/hw/top_earlgrey/doc/specification.html.)
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Read the top_earlgrey specification and the DV sequences in hw/top_earlgrey/dv/env/seq_lib, then compare them with the AES programmer's guide example. Document how module connections are made and how system-level programming can test IP interactions and RoT functionality. Done means a newcomer can follow the guide to understand and run these tests.
Written by the indexing model from the issue text.
Assessment
- Domain
- documentation, embedded-iot, security, testing-qa
- Issue type
- Documentation
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100