[top_darjeeling] Memory scrambling and ECC | undetected faults

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Initially discussed in issue #10976 and Security WG 2022-12-08 and 2022-03-03. Please see issue (bottom) for summary.
Conclusion:

• A change for integrated OT is highly recommended since single bit flips unscramble to multi-bit flips which are partly not detected and lead to silent data corruption which is not acceptable in the integrated setting (high-availability / server systems with one bit faults possible).

Current proposals on how to change for integrated:

• Switch order of ECC and scrambling so that ECC closer to storage. Similarly: Have memory ECC as the last function before storage including scrambling and potential bus integrity ECC.
• Remove permutation layer from scrambling to avoid single-to-multi-bit passing ECC issues.
• Add a single parity bit to the memory that is checked before the de-scrambling to cover single-bit memory corruption.
• Don’t feed the the ECC bits through the scrambling logic and instead separately compute how the ECC bits need to change for the scrambled/de-scrambled data. This allows checking the ECC right after reading out from memory AND again close to the CPU. The challenge is the non-linear S-Box layer in the scrambling (this is similar to a masking countermeasures against SCA). Not feeding the ECC bits through the scrambler can save some area as the scrambling becomes simpler (no longer applied to an odd number of bits).
• Note: Reliability concerns can partly be addressed by regularly flushing out caches using a fence.i instruction, reprogramming OTBN, and potentially hashing segments of RAM.

cc @neeraj-rv @vogelpi @GregAC @moidx @bilgiday @cdgori @msfschaffner @tjaychen

Start by reading issue #10976 and the cited Security WG discussions from 2022. The proposals need an architectural decision for integrated OpenTitan before implementation; done means the selected memory ECC and scrambling design detects the relevant single-bit faults without silent corruption.