[dvsim] DVSIM check X_PROP result
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Component:DV
Earlgrey-PROD Candidate
Tool:dvsim
- Dominant language
- SystemVerilog
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- Avg merge
- 2d 22h
- Merged PRs (30d)
- 141
Description
### Description
Based on the discussions and preparation for V2.5; it was suggested that there should be a DVSIM check for the result of the tools to see if X_PROP_ANALYSIS_COMPLETED can be signed-off.
Add a check in dvsim that ensures 100% instrumentation success and fails if <100%.
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by locating the DVSIM result-checking entry point and the handling of X_PROP_ANALYSIS_COMPLETED. Add a check that verifies 100% instrumentation success and fails below that threshold. Done means the DVSIM check can sign off only when instrumentation reaches 100%.
Written by the indexing model from the issue text.
Assessment
- Domain
- testing, tooling
- Issue type
- Feature
- Difficulty
- 2/5
- Estimated time
- 1-3 hours
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 45/100