Interacting with GPIO during Verlilator simulation
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- Dominant language
- SystemVerilog
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Description
Description
I am trying to run simulation using verilator with the bazel test command. After the simulation is started and when I am trying to pull some GPIO to high or low as mentioned in the documentation (using the FIFO Pipes) I always get an message prompt that "You are trying to pull an diasbled pin low/high". Could you please help me understand this?
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by reading the documentation's FIFO Pipes section and the Verilator simulation invoked by the bazel test command. Search for the exact disabled-pin message and trace how GPIO enable state is configured before a FIFO pull. Done means determining whether the documented setup is incorrect and documenting or correcting the required setup so GPIO changes are accepted.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot, testing-qa
- Issue type
- Bug
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100