lowRISC / lowRISC/opentitan

[tlul] TL-UL `data` zeroing inconsistencies

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Component:Security Earlgrey-PROD Candidate Hotlist:Silicon IP:rv_core_ibex IP:tlul SW:cryptolib Type:FutureRelease
Dominant language
SystemVerilog
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Description

Description

This is a spin-off from #16767 concerning the inconsistencies observed at TL-UL data port. In the earlier issue, there was a consensus that, all things considered, we would like to clear the value of data after a TL-UL transaction is completed (with an exception to entropy related data/randomness, @vogelpi).

Using the same waveform examples, notice the following highlighted inconsistencies:

Expected behavior:

  • 0x0 -> data -> 0x0 on any TL-UL data port (host or client)

Unexpected observation:

  • On the keymgr side, the TL-UL output data port is not cleared.
  • Sometimes data port is cleared to all 1s (observed at Ibex TL-UL input).
  • On Ibex side, the TL-UL output port is feeding some "garbage" values to data port, even though there is no transaction.

Screenshot from 2023-02-21 17-56-50
Screenshot from 2023-02-21 17-51-47

Contributor guide

Open the contributing guide

First steps

  1. Read the whole issue, then the project's contributing guide.
  2. Comment on the issue to say you are picking it up — it saves two people doing the same work.
  3. Fork the repository and make your change on a branch.
  4. Open a pull request that references the issue number.

Research direction

Start by reviewing the TL-UL data behavior shown in the waveform examples, including the keymgr and Ibex host/client paths. Trace where each data port is driven after a transaction completes. Done means non-entropy TL-UL data ports consistently return to 0x0 without exposing garbage or all-ones values.

Written by the indexing model from the issue text.

Assessment

Domain
embedded-iot, security
Issue type
Bug
Difficulty
4/5
Estimated time
3-5 days
Activity status
Stale
Clarity
Mostly clear
Newbie friendliness
25/100

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