[tlul] TL-UL `data` zeroing inconsistencies
Nobody has claimed this yet.
- Dominant language
- SystemVerilog
- Stars
- 3.6k
- Forks
- 1.1k
- Avg merge
- 2d 22h
- Merged PRs (30d)
- 141
Description
Description
This is a spin-off from #16767 concerning the inconsistencies observed at TL-UL data port. In the earlier issue, there was a consensus that, all things considered, we would like to clear the value of data after a TL-UL transaction is completed (with an exception to entropy related data/randomness, @vogelpi).
Using the same waveform examples, notice the following highlighted inconsistencies:
Expected behavior:
- 0x0 -> data -> 0x0 on any TL-UL data port (host or client)
Unexpected observation:
- On the keymgr side, the TL-UL output data port is not cleared.
- Sometimes data port is cleared to all 1s (observed at Ibex TL-UL input).
- On Ibex side, the TL-UL output port is feeding some "garbage" values to data port, even though there is no transaction.


Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by reviewing the TL-UL data behavior shown in the waveform examples, including the keymgr and Ibex host/client paths. Trace where each data port is driven after a transaction completes. Done means non-entropy TL-UL data ports consistently return to 0x0 without exposing garbage or all-ones values.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot, security
- Issue type
- Bug
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 25/100