[doc] Add human-readable names and descriptions to remaining blocks
Nobody has claimed this yet.
- Dominant language
- SystemVerilog
- Stars
- 3.6k
- Forks
- 1.1k
- Avg merge
- 2d 22h
- Merged PRs (30d)
- 141
Description
Add a human-readable name as well as one-line and one-paragraph descriptions to the remaining hardware blocks, including those specific to a top (`ast`, `sensor_ctrl`, `alert_handler`, and `rv_plic`).
Draft document here: https://docs.google.com/document/d/1nX0GiXE6W5PEEGGwiCCToCwq19nCBpVRDtmN5f_0paQ/edit
What about primitives? And what about TL-UL?
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start with the linked draft document and review the remaining hardware blocks, including ast, sensor_ctrl, alert_handler, and rv_plic. Determine how primitives and TL-UL should be handled, then add a human-readable name plus one-line and one-paragraph descriptions for the agreed scope. Done means the remaining blocks are documented and those scope questions are resolved.
Written by the indexing model from the issue text.
Assessment
- Domain
- documentation
- Issue type
- Documentation
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 35/100