Parse SystemVerilog with a proper parser
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- Dominant language
- SystemVerilog
- Stars
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- Avg merge
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Description
We have some places in our code where we hackishly/partially parse (parts of) SystemVerilog. It would be nice to choose an existing parser and integrate it properly into the codebase.
Currently we partially parse SV in these places:
primgen.pyutil/fpvgen/sv_parse.py
primgen.py also contains a list of parsers which have already been tested in the past and weren't up for the job at this point, but could still be a good starting point to extend/contribute to.
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by reading the partial SystemVerilog parsing in primgen.py and util/fpvgen/sv_parse.py, then review the parser list in primgen.py. Done means selecting an existing parser and integrating it properly into the codebase in place of the current partial parsing.
Written by the indexing model from the issue text.
Assessment
- Domain
- tooling
- Issue type
- Feature
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100