[topgen] Topgen fails if all source clocks are free running
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- SystemVerilog
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Description
### Description
I was trying no generate a new toplevel in which the source clocks would be external and free running, although derived clocks would still be managed.
The topgen however cannot populate the parent_child_clks dict because of lines 321 and 322 of util/topgen/clocks.py :
`if not clk.aon:`
` parent_child_clks[name] = [name];`
I'm not sure if the field 'aon' is being used correctly or if external free-running source clocks are not allowed in the design as-is since there is an overlap in the meaning of the hjson field 'aon' for free-running clocks and the defined low-power 'aon' always-on clock.
Would just like to understand the rationale.
Thanks
Contributor guide
Research direction
Start in util/topgen/clocks.py at lines 321-322 and trace how the parent_child_clks dictionary is populated for source clocks. Reproduce topgen with external, free-running source clocks, then determine the intended relationship between the hjson aon field and free-running clocks; done means the behavior or required restriction is clearly established and the failure is addressed.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- python
- Domain
- tooling
- Issue type
- Bug
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 35/100