[top_darjeeling] Code execution support from SRAM not internal to OT subsystem

desc

If we need to support code execution from memories outside of the OT subsystem, there are a few things to consider:

1. How is access to the external memory access controlled and how is OT involved in those controls?
2. Do we need confidentiality, integrity and potentially freshness protection?
   • If yes, this protection can either be implemented on the host side or the destination side.

Host side implies the OT subsystem verifies and decrypts instructions on the fly. This can be implemented using a simple mechanism or something more full blown like full memory encryption.

In the simple case, the minimum "block" size would need to be considered. We would then need to consider how the crypto blocks would be utilized in such a scheme and how to arbitrate these crypto blocks separately from generic software usage.

In the more full blown memory encryption case, we would need a full scheme that guarantees confidentiality, integrity and freshness.

Destination side implies something similar to what OT has done thus far, memory scrambling and integrity checking. This is much lighter overhead but would require host role IDs to be known such that keys can be switched on the fly.