[top_darjeeling] Clock / Power / Reset Integration
Open
@neeraj-rv is already working on this.
Since Jan 18, 2023.
Component:Darjeeling
Earlgrey-PROD Triaged
- Dominant language
- SystemVerilog
- Stars
- 3.6k
- Forks
- 1.1k
- Avg merge
- 2d 22h
- Merged PRs (30d)
- 141
Description
desc
Need to examine for the integrated use case, how the clock / power / reset integration changes.
- Is it safe to make the same assumptions regarding power up? Can we assume the regulators / clocks necessary are available? Does the sequence need to change?
- Can we assume a similar clocking structure where existing clock enables could turn clocks off in a similar way
- For resets, what can we assume about the outside world in terms of reset control hook-ups and reset feedback?
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Assessment
This issue has not been assessed yet.