[chip-test] chip_sw_rv_core_ibex_alerts

@GregAC is already working on this.

Since Apr 18, 2023.

### Test point name

[chip_sw_rv_core_ibex_alerts](https://github.com/lowRISC/opentitan/blob/316831f8c2199f2288dd57ac4aeaec3334b5dfb8/hw/top_earlgrey/data/chip_testplan.hjson#L3271)

### Host side component

SystemVerilog + Rust

### OpenTitanTool infrastructure implemented

Yes

### Silicon Validation (SiVal)

Yes

### Emulation targets
- [ ] None
- [ ] CW310
- [ ] Hyperdebug + CW310

### Contact person

@gregac

### Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.
- [ ] Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
- [ ] Device-side (C) component developed
- [ ] Bazel build rules developed
- [ ] Host-side component developed
- [ ] Test added to dvsim nightly regression (and passing at time of checking)
- [ ] For SiVal test cases, test is running relevant FPGA or silicon regression

Note that this testplan entry seeks to cover all alerts signaled at `ibex_top` and at `rv_core_ibex` levels.

> estimate 16