[chip-test] chip_sw_tap_strap_sampling
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- Dominant language
- SystemVerilog
- Stars
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Description
### Test point name
[chip_sw_tap_strap_sampling](https://github.com/lowRISC/opentitan/blob/316831f8c2199f2288dd57ac4aeaec3334b5dfb8/hw/top_earlgrey/data/chip_testplan.hjson#L475)
### Host side component
SystemVerilog
### OpenTitanTool infrastructure implemented
None
### Contact person
sriyerg
### Checklist
This test is already developed. This issue tracks the effort to enhance it for V3. The pending work item is referenced in the link to the testplan above:
```
Verify loss of DFT functionality when DFT straps are deasserted on the next POR cycle.
```
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start with the chip_sw_tap_strap_sampling entry in hw/top_earlgrey/data/chip_testplan.hjson and locate the already-developed SystemVerilog test it references. Confirm the V3 expectation for the next POR cycle, then run the existing test and extend its checks so completion demonstrates loss of DFT functionality when DFT straps are deasserted.
Written by the indexing model from the issue text.
Assessment
- Domain
- testing-qa
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 42/100