[dv/jtag] Enable flow to verify the openOCD debugger in simulation
- Dominant language
- SystemVerilog
- Stars
- 3.6k
- Forks
- 1.1k
- Avg merge
- 2d 22h
- Merged PRs (30d)
- 141
Description
A flow to use jtag in simulation is created in https://github.com/lowRISC/opentitan/pull/16486. The code snipppets used to access jtag in silicon could be different than the snippets generated in by the DV flow, which could be problematic if we are unable to reproduce in dv issues found in silicon.
It would be desirable to have some way to either compare the silicon vs. DV sequences, or to feed the silicon sequences directly to the dv flow.
Contributor guide
Research direction
Start by reviewing PR #16486, which created the JTAG simulation flow, and compare the silicon access snippets with those generated by the DV flow. Done should provide a way to compare the sequences or feed the silicon sequences directly into DV so silicon issues can be reproduced.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot, testing-qa
- Issue type
- Feature
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100