//sw/device/tests:chip_power_sleep_load_sim_verilator hangs

This PR affects a verilator test that times out.

Test appears to stop making progress after printing:
```
I00006 chip_power_sleep_load.c:338] PWM active
```

Maybe the OTP isn't properly configured for the verilator test and otp_ctrl is hanging?
Or maybe it's getting configured and servicing the checks is preventing the test from making progress?

_Originally posted by @drewmacrae in https://github.com/lowRISC/opentitan/issues/16541#issuecomment-1343165772_

Reproduce //sw/device/tests:chip_power_sleep_load_sim_verilator and confirm that it stops after the “PWM active” message at chip_power_sleep_load.c:338. Inspect the Verilator test’s OTP configuration and whether servicing the checks prevents progress. Done means the test completes without timing out.

Written by the indexing model from the issue text.