[chip-test] Move C tests without external host from tests/sim_dv/ to tests/

Here is some guidance for where the C test should reside.
1. If the C test needs an external host, or needs the DV sequence to drive IOs, or needs the DV sequence to force internal signals, put the C test under `tests/sim_dv`, otherwise, put it under `tests/` so that it can run with FPGA and Verilator.
2. If a DV sequence is only used for passive checking, the C test should be put in `tests`
3. If a small port of code can only run in DV, e.g. C test relies on the DV sequence to pass expected results for check, we could use flag `kDeviceSimDV`. And the C test can be put in `tests`. This is an [example](https://cs.opensource.google/opentitan/opentitan/+/master:sw/device/tests/keymgr_sideload_kmac_test.c;l=86?q=kDeviceSimDV&start=11).

We may be able to move some of the tests from `tests/sim_dv` to `tests`. I categorize them based on the block name. The person who is familiar with the test may be able to look into it.

- alert handler
- [ ] [alert_handler_entropy_test.c](https://cs.opensource.google/opentitan/opentitan/+/master:sw/device/tests/sim_dv/alert_handler_entropy_test.c)
- [ ] [alert_handler_escalation.c](https://cs.opensource.google/opentitan/opentitan/+/master:sw/device/tests/sim_dv/alert_handler_escalation.c)
- CSRNG
- [ ] [csrng_fuse_en_sw_app_read.c](https://cs.opensource.google/opentitan/opentitan/+/master:sw/device/tests/sim_dv/csrng_fuse_en_sw_app_read.c)
- [ ] [csrng_lc_hw_debug_en_test.c](https://cs.opensource.google/opentitan/opentitan/+/master:sw/device/tests/sim_dv/csrng_lc_hw_debug_en_test.c)
- Entropy_src
~- [ ] [entropy_src_fuse_en_fw_read_test.c](https://cs.opensource.google/opentitan/opentitan/+/master:sw/device/tests/sim_dv/entropy_src_fuse_en_fw_read_test.c)~ Test removed with #21118
- flash_ctrl

- [x] [flash_ctrl_lc_rw_en_test.c](https://cs.opensource.google/opentitan/opentitan/+/master:sw/device/tests/sim_dv/flash_ctrl_lc_rw_en_test.c)
- [x] [flash_escalation_reset_test.c](https://cs.opensource.google/opentitan/opentitan/+/master:sw/device/tests/sim_dv/flash_escalation_reset_test.c)
- [x] ~[flash_init_test.c](https://cs.opensource.google/opentitan/opentitan/+/master:sw/device/tests/sim_dv/flash_init_test.c)~ not applicable
- [x] ~[flash_rma_unlocked_test.c](https://cs.opensource.google/opentitan/opentitan/+/master:sw/device/tests/sim_dv/flash_rma_unlocked_test.c)~ not applicable
- otp/lc_ctrl

- [ ] [otp_ctrl_lc_signals_test.c](https://cs.opensource.google/opentitan/opentitan/+/master:sw/device/tests/sim_dv/otp_ctrl_lc_signals_test.c)
- pwrmgr (exclude pwmgr_*glitch* test because they need to glitch internal signals, exclude pwrmgr_b2b_sleep_reset_test since it requires very precise alignment of wakeup and reset)

- [x] [pwrmgr_deep_sleep_all_reset_reqs_test.c](https://cs.opensource.google/opentitan/opentitan/+/master:sw/device/tests/sim_dv/pwrmgr_deep_sleep_all_reset_reqs_test.c)
- [x] [pwrmgr_deep_sleep_all_wake_ups.c](https://cs.opensource.google/opentitan/opentitan/+/master:sw/device/tests/sim_dv/pwrmgr_deep_sleep_all_wake_ups.c)
- [x] [pwrmgr_normal_sleep_all_reset_reqs_test.c](https://cs.opensource.google/opentitan/opentitan/+/master:sw/device/tests/sim_dv/pwrmgr_normal_sleep_all_reset_reqs_test.c)
- [x] [pwrmgr_normal_sleep_all_wake_ups.c](https://cs.opensource.google/opentitan/opentitan/+/master:sw/device/tests/sim_dv/pwrmgr_normal_sleep_all_wake_ups.c)
- [x] [pwrmgr_random_sleep_all_reset_reqs_test.c](https://cs.opensource.google/opentitan/opentitan/+/master:sw/device/tests/sim_dv/pwrmgr_random_sleep_all_reset_reqs_test.c)
- [x] [pwrmgr_random_sleep_all_wake_ups.c](https://cs.opensource.google/opentitan/opentitan/+/master:sw/device/tests/sim_dv/pwrmgr_random_sleep_all_wake_ups.c)
- sram_ctrl

- [ ] [sram_ctrl_execution_main_test.c](https://cs.opensource.google/opentitan/opentitan/+/master:sw/device/tests/sim_dv/sram_ctrl_execution_main_test.c)
- [ ] [sram_ctrl_scrambled_access_test.c](https://cs.opensource.google/opentitan/opentitan/+/master:sw/device/tests/sim_dv/sram_ctrl_scrambled_access_test.c)

[Effort estimate](https://github.com/lowRISC/opentitan/issues/16636#issuecomment-1482749146_) by @gdessouky for `lc_ctrl`:
> estimate 2

Start with the placement guidance and inspect the unchecked C tests under sw/device/tests/sim_dv, especially the alert handler, CSRNG, otp/lc_ctrl, and sram_ctrl files. Check whether each needs an external host, DV-driven IO, or forced internal signals; done means eligible tests are moved to tests/ and continue to run with FPGA and Verilator, while the listed exceptions remain in sim_dv.

Written by the indexing model from the issue text.