[dv, dpi] UART logfile location can't be specified via chip_sim.core

UART log file location supposedly can be set via dv plusarg with https://github.com/lowRISC/opentitan/blob/37529086399d5e328bdc814175167e76fcd0437d/hw/dv/dpi/uartdpi/uartdpi.sv#L41

And its setting should be configurable via
https://github.com/lowRISC/opentitan/blob/37529086399d5e328bdc814175167e76fcd0437d/hw/top_earlgrey/dv/verilator/chip_sim.core#L61-L64

Aside from the typo of `UART_LOG_uart0` --> `UARTDPI_LOG_uart0` and `datatype: string` --> `datatype: str`, How to set the value properly and pass it down to uartdpi.sv? Should an additional entry added to https://github.com/lowRISC/opentitan/blob/37529086399d5e328bdc814175167e76fcd0437d/hw/top_earlgrey/dv/verilator/chip_sim.core#L77

such as
```
- UARTDPI_LOG_uart0=/tmp/uart0.log
```
I tried to add that but the verilator run shows no change and the default log file name still applied
https://github.com/lowRISC/opentitan/blob/37529086399d5e328bdc814175167e76fcd0437d/hw/dv/dpi/uartdpi/uartdpi.sv#L17

Start by tracing the UARTDPI_LOG_uart0 plusarg in hw/dv/dpi/uartdpi/uartdpi.sv and its configuration in hw/top_earlgrey/dv/verilator/chip_sim.core, including the referenced lines and entries. Run the Verilator chip simulation with the configured value and verify that the UART output is written to the requested path instead of the default log file.

Written by the indexing model from the issue text.