[chip-test] chip_sw_keymgr_sideload_kmac_error

### Test point name

[chip_sw_keymgr_sideload_kmac_error](https://cs.opensource.google/opentitan/opentitan/+/master:hw/top_earlgrey/data/chip_testplan.hjson?q=chip_sw_keymgr_sideload_kmac_error&ss=opentitan%2Fopentitan:hw%2F)

### Host side component

SystemVerilog

### OpenTitanTool infrastructure implemented

_No response_

### Contact person

@tjaychen, @eunchan, @weicai

### Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.
- [ ] Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
- [ ] Device-side (C) component developed
- [ ] Bazel build rules developed
- [ ] Host-side component developed
- [ ] HJSON test plan updated with test name (so it shows up in the dashboard)
- [ ] Test added to dvsim nightly regression (and passing at time of checking)

Start with the linked chip_testplan.hjson entry for chip_sw_keymgr_sideload_kmac_error and check whether existing tests already cover it. Work through the checklist for the device-side C component, Bazel rules, host-side SystemVerilog component, test-plan update, and dvsim nightly regression; done means the test is included and passing.

Written by the indexing model from the issue text.