[chip-test] chip_sw_lc_ctrl_kmac_error

### Test point name

[chip_sw_lc_ctrl_kmac_error](https://github.com/lowRISC/opentitan/blob/72211c306ccacc11da7f4f2059c291690abcf9de/hw/top_earlgrey/data/chip_testplan.hjson#L1712)

### Host side component

SystemVerilog / Rust

### OpenTitanTool infrastructure implemented

Yes

### Silicon Validation (SiVal)

Yes

### Emulation targets
- [ ] None
- [ ] CW310
- [ ] Hyperdebug + CW310

### Contact person

### Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.
- [ ] Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
- [ ] Device-side (C) component developed
- [ ] Bazel build rules developed
- [ ] Host-side component developed
- [ ] Test added to dvsim nightly regression (and passing at time of checking)
- [ ] For SiVal test cases, test is running relevant FPGA or silicon regression