[rtl,reset] Improve handling of main domain power glitches

Nobody has claimed this yet.

A voltage glitch in the main power domain should be handled more clearly. In response to such a glitch the power manager should detect it and request resets to other chip components as needed. The current implementation has rstmgr detecting the glitch, and informing power manager via one of its reset outputs, so in a way it creates a cyclic dependency, since reset outputs are in response to pwrmgr or AON por_n, except in this niche case.

In terms of cleaning up the pwrmgr/rstmgr interface we could move por_n_i[1] (which indicates a main power glitch) to the pwrmgr, and make it the sole responsible for detecting and handling power glitches, and have rstmgr simply respond to them.

Another somewhat related problem arises with the handshake between pwrmgr and ast regarding clock enables via the *clk_en and *clk_val:
- The handshake is typically initiated by pwrmgr when it needs to turn off the clocks by clearing *clk_en, in which case the expectation is that *clk_val should end up dropping (viceversa when pwrmgr starts the clocks).
- But in response to a main power glitch the AST can decide to turn off the clocks driving *clk_val down, and pwrmgr's *clk_en should drop in response.

We have assertions covering these cases, and they can get confused because they have no way to determine what unit is meant to cause the drop. This could be resolved if the assertions also got por_n_i, since a drop in por_n_i[1] is the signature of a main power glitch.

Start by tracing the pwrmgr, rstmgr, and AST interfaces, especially por_n_i[1] and the *clk_en/*clk_val handshake. Review the existing assertions covering clock changes during main power glitches. Done means pwrmgr is solely responsible for detecting and handling the glitch, rstmgr responds to it, and the assertions distinguish glitch-driven changes from pwrmgr-initiated ones.

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