lowRISC / lowRISC/opentitan

[ast] Check whether AST register map can be autogenerated instead of checking it in

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SystemVerilog
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Description

The AST register table seems to be checked into the repo at the moment:
https://github.com/lowRISC/opentitan/blob/master/hw/top_earlgrey/ip/ast/doc/ast_regs.html

We should consider making this fully autogenerated as all other comportable IPs.

This is not urgent, I have hence moved this to M3.

CC @tjaychen @arnonsha @Jacob-Levy

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First steps

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  3. Fork the repository and make your change on a branch.
  4. Open a pull request that references the issue number.

Research direction

Start with hw/top_earlgrey/ip/ast/doc/ast_regs.html and compare how the other comportable IPs generate their register maps. Determine the automation path and what repository artifacts should remain; done means the AST register table is generated consistently rather than checked in manually.

Written by the indexing model from the issue text.

Assessment

Domain
build-system, embedded-iot
Issue type
Feature
Difficulty
4/5
Estimated time
3-5 days
Activity status
Stale
Clarity
Needs clarification
Newbie friendliness
35/100

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