lowRISC / lowRISC/opentitan

[util/tlgen] Allow user to specify async fifo depth

Open
#15,754 0 comments 0 reactions 0 assignees View on GitHub
Earlgrey-PROD Triaged Type:FutureRelease
Dominant language
SystemVerilog
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Avg merge
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Merged PRs (30d)
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Description

The asycn fifo depth inside tlgen is hardcoded right now, but it would be good if in the future top levels can specify how deep it should be directly.

Contributor guide

Open the contributing guide

Research direction

Start by locating tlgen and the hardcoded async FIFO depth, then trace how top-level configuration is represented and passed into generated output. Done means a top level can specify the FIFO depth directly and tlgen uses that value instead of the hardcoded depth.

Written by the indexing model from the issue text.

Assessment

Domain
embedded-iot, tooling
Issue type
Feature
Difficulty
4/5
Estimated time
3-5 days
Activity status
Stale
Clarity
Needs clarification
Newbie friendliness
25/100

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