[util/tlgen] Allow user to specify async fifo depth
Open
Earlgrey-PROD Triaged
Type:FutureRelease
- Dominant language
- SystemVerilog
- Stars
- 3.6k
- Forks
- 1.1k
- Avg merge
- 2d 22h
- Merged PRs (30d)
- 141
Description
The asycn fifo depth inside tlgen is hardcoded right now, but it would be good if in the future top levels can specify how deep it should be directly.
Contributor guide
Research direction
Start by locating tlgen and the hardcoded async FIFO depth, then trace how top-level configuration is represented and passed into generated output. Done means a top level can specify the FIFO depth directly and tlgen uses that value instead of the hardcoded depth.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot, tooling
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100