Primitives to hold errors high until reset
- Dominant language
- SystemVerilog
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Description
A potential security issue in OTBN was discovered where some errors triggered by a fault being detected only asserted their error signal for a single cycle. When this occurred along with an OTBN start command this would allow the fault to be missed. The fix was to latch various errors, so once an error signal is raised it stays raised. See this PR for more detail: https://github.com/lowRISC/opentitan/pull/15611
We should consider introducing primitives to handle this.
1. Create a `prim_hold` or `prim_err_latch` or similar which implements the set and only clear on reset behaviour
2. Add this behaviour to `prim_count` for its error output (in OTBN most of the issues were around the counter error only being asserted for a single cycle, though this was because the count was being cleared the same cycle the fault was being injected).
This isn't an M2 issue, but something to consider for the future
@tjaychen @cdgori @moidx
Contributor guide
Research direction
Start by reading PR #15611 and the existing prim_count implementation, then compare the OTBN error cases described in this issue. Done means defining an agreed prim_hold or prim_err_latch primitive and determining how prim_count should retain its error output until reset.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot, security
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 35/100