[spi_device] Late CSb de-assertion for op-complete commands
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@a-will is already working on this.
Since Jan 12, 2024.
Component:RTL
Earlgrey-PROD Candidate
IP:spi_device
Priority:P3
- Dominant language
- SystemVerilog
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Description
The current SPI_DEVICE HWIP has a few limitation of detecting the host system's misbehaviors:
- If host de-asserts CSb prior to the full 8 bit opcode, HW IP silently drops
- If host de-assrets CSb later than 8th beat, but the received opcode expects op-complete command (such as chip erase), it is expected to discard the command. The current version of SPI_DEVICE, if host terminates the command at 9th beat ~15th beat, the HW uploads the opcode but does not report any errors.
CC: @tjaychen @a-will @weicaiyang @jeoongp
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