[dv] time based dumps?
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- SystemVerilog
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Description
should we consider adding dvsim options to control when dumps should turn on/off?
Some of the longer sims (especially those involving bootstrap), don't always have something interesting to debug until a certain point in time.
I took a look around, and i don't really if the right answer is to add another dvsim argument and pass it all the way through (as environment variables to sim.tcl?), or if there's a smarter way.
I'm honestly also fine with just hacking waves.tcl for now if that's a quick way to do this.
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by reviewing the existing dvsim options and the dump handling in waves.tcl, then trace how simulation settings reach sim.tcl, including the possible environment-variable path mentioned in the issue. The work is done when a simulation can control when dumps turn on and off by time without requiring a manual waves.tcl hack.
Written by the indexing model from the issue text.
Assessment
- Domain
- testing
- Issue type
- Feature
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100