[dv/csr] Handle reset in the middle of CSR transactions
- Dominant language
- SystemVerilog
- Stars
- 3.6k
- Forks
- 1.1k
- Avg merge
- 2d 22h
- Merged PRs (30d)
- 141
Description
The DV code dealing with CSR accesses gets confused if a reset happens while there is an ongoing CSR access. In order to avoid this confusion tests are restricted to avoid resets while there are ongoing CSR accesses. This is undesirable on two accounts:
- It prevents testing IP unit behavior when it gets reset in the middle of a CSR access, which is a pretty realistic scenario.
- It complicates the generation of testing scenarios in order to prevent these cases.
Contributor guide
Research direction
No file or test paths are named. Locate the DV CSR-access handling and the tests that currently exclude resets during ongoing CSR accesses; first reproduce a reset during a CSR transaction. Done means the DV logic remains consistent through the reset and scenarios no longer need to forbid this case.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot, testing-qa
- Issue type
- Bug
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 35/100