[SPI_Host] Flash BFM Integration

To ensure SPI_Host compatibility with the desired flash chip we should bring in the BFM model (SystemVerilog) and ensure that it interacts with SPI in the desired manner.
For further details see - https://docs.opentitan.org/hw/ip/spi_host/doc/

The flash chip that we intend to get working with OT and want to ensure we have compatibility before generating the RTL freeze is W25Q01JV.
Further details available at - https://www.winbond.com/hq/product/code-storage-flash-memory/serial-nor-flash/?__locale=en&partNo=W25Q01JV
In particular the model is available at https://www.winbond.com/hq/support/documentation/?__locale=en&line=/product/code-storage-flash-memory/index.html&family=/product/code-storage-flash-memory/serial-nor-flash/index.html&pno=W25Q01JV&category=/.categories/resources/verilog-model/

The model is closed source so part of the effort will be in determining how we can get the model used in CI without breaking the terms of the licence.
Suggestion would be looking at the private CI instances that are used for EDA tooling / licenses and having the model integrated at that point.

estimate 16
Corresponds to SH:2 on internal tracking