[chip dv] Do not use cfg.clk_rst_vif.wait_clks() to wait for clock cycles

We need to replace the `cfg.clk_rst_if.wait_clks()` invocations in our test sequences with the appropriate clk / rst monitor in `chip_if ` for example, `cfg.chip_vif.sys_clk_rst_if.wait_clks()`.

The reason for this is explained in this commit: https://github.com/lowRISC/opentitan/pull/14917/commits/bb2bb8abf3cefcb5bb0b25680b6c74051809e5cb

Previously, the `wait_clks` on this would wait on the external clock source, which was unsed in most tests, so it was incorrect all along. As of the commit above, the clock port of this interface is unconnected. The clock remains active to prevent breakages.

Search the chip DV test sequences for cfg.clk_rst_if.wait_clks() invocations, then inspect the appropriate clock/reset monitor in chip_if and the referenced commit for the intended mappings. Replace each use with the relevant monitor wait and run the affected chip DV tests to confirm that all clock-cycle waits use connected interfaces.

Written by the indexing model from the issue text.