[prim_esc_receiver] output status
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Earlgrey-PROD Triaged
Type:Enhancement
- Dominant language
- SystemVerilog
- Stars
- 3.6k
- Forks
- 1.1k
- Avg merge
- 2d 22h
- Merged PRs (30d)
- 141
Description
Discussed with Tim, and we think it would be nice to have `prim_esc_receiver` to output its status in case something went out of sync.
Consider output: the enablement of the ping reverse timeout counter.
@tjaychen @msfschaffner
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by locating the prim_esc_receiver module and reading how the ping reverse timeout counter is enabled. Determine how its status could be exposed and inspect the associated verification for an existing interface or expected behavior. Done means the receiver reports whether that counter is enabled and the behavior is covered by verification.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot, security
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 35/100