[opentitantool] Consider adding the CRC check back to update-usr-access command
Open
Component:Software
Priority:P3
SW:Build System
SW:opentitantool
Type:Task
- Dominant language
- SystemVerilog
- Stars
- 3.6k
- Forks
- 1.1k
- Avg merge
- 2d 22h
- Merged PRs (30d)
- 141
Description
#14877 adds the `update-usr-access` to `opentitantool` and uses it in `bitstream_splice` to improve local workflows that involve splicing a locally built `rom` or `test_rom` into a bitstream from the GCS bucket. See #14865 for details.
One particular shortcoming of the implementation in #14877 is that it disables the CRC check during FPGA programming. We should consider enabling it again.
Contributor guide
Research direction
Start with the update-usr-access implementation from #14877 and its use in bitstream_splice; inspect where FPGA programming disables the CRC check. Done means the command path restores CRC checking while preserving the local rom/test_rom splice workflow.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- google-cloud
- Domain
- embedded-iot, tooling
- Issue type
- Feature
- Difficulty
- 3/5
- Estimated time
- 1-2 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 45/100