[doc] Clean up hard-coded intersignal tables in all IP specs
- Dominant language
- SystemVerilog
- Stars
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- Avg merge
- 2d 22h
- Merged PRs (30d)
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Description
Docgen is now able to automatically generate description tables for the intersignals specified in the IP Hjson files.
This obviates the need to maintain hardcoded tables for these signals in the IP specs.
We should go through all specs and clean this up.
A similar cleanup should probably be done for the instantiation parameters as well.
CC @tjaychen @moidx @eunchan @vogelpi @GregAC
Contributor guide
Research direction
Start by reviewing the IP specs and the Docgen behavior that generates intersignal description tables. Identify each hard-coded intersignal table and remove the redundant copies across the specs; check whether instantiation-parameter tables are included in the intended cleanup. Done means the specs rely on generated tables without losing required documentation.
Written by the indexing model from the issue text.
Assessment
- Domain
- documentation
- Issue type
- Documentation
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 35/100