[dv] Create separate core file for DUT hierarchy include files
- Dominant language
- SystemVerilog
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- 2d 22h
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Description
We currently define hierarchy paths using SV macros at the chip and block-level. Ideally, the block-level include files should be reusable in the chip-level environment.
However, due to the way the dependencies are currently structured in our fusesoc build flow, the block-level include files are compiled before the chip-level include files. Therefore, the chip-level paths are not yet defined when evaluating the block-level macros.
A way to work around this issue is to use a fusesoc flag to force a different compilation order - i.e., the following conditional dependency can be added to the core file containing the block-level svh file:
```
[...]
depend:
- "fileset_top ? (lowrisc:dv:chip_sim)"
- [...]
[...]
```
While this works, it is not a very clean. A more elegant solution would be to create a separate core file for an sv source that only contains DUT hierarchies.
Contributor guide
Research direction
Start by tracing the core file containing the block-level SVH file and its FuseSoC dependencies, especially the fileset_top dependency on lowrisc:dv:chip_sim. Create a separate core file for an SV source containing only the DUT hierarchies, then verify that block-level include files remain reusable in the chip-level environment without relying on a forced compilation order.
Written by the indexing model from the issue text.
Assessment
- Domain
- build-system, embedded-iot
- Issue type
- Refactor
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 35/100