[prim] Latch Enable signal for Sparse FSM macro
Open
Earlgrey-PROD Triaged
- Dominant language
- SystemVerilog
- Stars
- 3.6k
- Forks
- 1.1k
- Avg merge
- 2d 22h
- Merged PRs (30d)
- 141
Description
`prim_flop_macros.sv` defines `PRIM_FLOP_SPARSE_FSM()` macro. It makes the sparse fsm FFs simple. However, the `prim_sparse_fsm_flop` module does not have a latch enable signal, which is useful in certain cases.
This issue is to track the enhancement:
- Add `latch_en` port in `prim_sparse_fsm_flop` module
- Revise `PRIM_FLOP_SPARSE_FSM()` macro to have optional `__en` argument, (default tied to 1'b1).
Contributor guide
Assessment
This issue has not been assessed yet.