[dv/chip] chip_sw_alert_handler_entropy test avoid external force
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Component:DV
Earlgrey-PROD Candidate
Priority:P2
Type:Enhancement
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- SystemVerilog
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Description
The chip level test `chip_sw_alert_handler_entropy` intends to check if all the pings can be triggered in the simulation.
To ensure that happens in the current design, we force the `wait_cyc_mask_i` value with SV sequence.
A better way would be to reseed the `LFSR` seed in every run time.
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