lowRISC / lowRISC/opentitan

[rv_core_ibex] Consider ICache pinning

Open
#14,510 5 comments 0 reactions 0 assignees View on GitHub
Component:RTL Component:Security Earlgrey-PROD Triaged Hotlist:Silicon IP:rv_core_ibex Priority:P2 Type:FutureRelease
Dominant language
SystemVerilog
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Description

The Ibex ICache currently has no pinning functionality. For security critical code to avoid timing side channels it may be advisable to disable the icache and execute straight from flash.

This has been deemed sufficient for the OpenTitan discrete use case but for integrated it may not work. The memory Ibex is executing from could have higher latency or variable timing. Here ICache pinning, allowing a particular section of code to be held in the ICache may be required.

An alternative solution would be a tightly coupled memory with fixed timing that Ibex could copy to and execute security critical code from.

Contributor guide

Open the contributing guide

Research direction

No files, tests, or entry points are named. Start by locating the rv_core_ibex ICache implementation and its existing timing or security tests, then clarify whether the expected outcome is ICache pinning or tightly coupled memory support and how completion will be verified.

Written by the indexing model from the issue text.

Assessment

Domain
embedded-iot, security
Issue type
Feature
Difficulty
5/5
Estimated time
Over a week
Activity status
Stale
Clarity
Needs clarification
Newbie friendliness
20/100

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