[top] "rom" interface of "rv_dm" is not a memory in top_earlgrey.hjson

Nobody has claimed this yet.

Noticed this while working on #14336 and discussed offline with @tjaychen. Currently, the entry for rv_dm [here](https://github.com/lowRISC/opentitan/blob/1447b4853447dffbc0193b5aab27d96012f950ff/hw/top_earlgrey/data/top_earlgrey.hjson#L572) looks like this:

```
{ name: "rv_dm",
type: "rv_dm",
clock_srcs: {clk_i: "main"},
clock_group: "infra",
reset_connections: {rst_ni: "lc"},
param_decl: {
IdcodeValue: "jtag_id_pkg::JTAG_IDCODE",
}
// Note that this module also contains a bus host.
base_addrs: {rom: "0x00010000", regs: "0x41200000"}
},
```
which doesn't create a memory.

As a result, it is not included in the return value of `TopGenC::memories()` and required a minor workaround in #14336.

Open hw/top_earlgrey/data/top_earlgrey.hjson and inspect the rv_dm entry's base_addrs alongside the logic used by TopGenC::memories(). Confirm the corrected representation causes the rom interface to appear in TopGenC::memories(), without needing the workaround noted in #14336.

Written by the indexing model from the issue text.