[chip-test] chip_usb_sof

### Test point name

[chip_usb_sof] (https://github.com/lowRISC/opentitan/blob/master/hw/top_earlgrey/data/chip_testplan.hjson#L315)

### Host side component

SystemVerilog

### OpenTitanTool infrastructure implemented

Unknown

### Contact person

@a-will

### Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.
- [ ] Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
- [ ] Device-side (C) component developed
- [ ] Bazel build rules developed
- [ ] Host-side component developed
- [ ] HJSON test plan updated with test name (so it shows up in the dashboard)
- [ ] Test added to dvsim nightly regression (and passing at time of checking)

Start with the chip_usb_sof entry in hw/top_earlgrey/data/chip_testplan.hjson and check whether an existing test covers it. Then determine the required device-side C, Bazel, host-side SystemVerilog, test-plan, and dvsim regression work listed in the checklist. Done means the checklist is completed and the test passes nightly regression.

Written by the indexing model from the issue text.