[fpga] Hyperdebug integration on FPGA targets
Open
Component:FPGA
Earlgrey-PROD Candidate
Priority:P2
Type:Task
- Dominant language
- SystemVerilog
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Description
This issue is to track the tasks required to enable Hyperdebug integrations on FPGA targets. Currently, host I/O connectivity is routed to the onboard SM3x in the CW310 board. We need an alternate FPGA pinout configuration to start Hyperdebug enablement.
Ideally the alternate pin configuration will be available in the repository, and Bazel/Fusesoc should be able to select between the available pinout configurations.
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Assessment
This issue has not been assessed yet.