lowRISC / lowRISC/opentitan

[chip, dv] Some pad IO are forced in vseq

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Component:ChipLevelTest
Dominant language
SystemVerilog
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Description

@sriyerg

The chip-level sysrst test directly forces the pad IO in this PR https://github.com/lowRISC/opentitan/pull/13216. I think it may be OK for now.
Once we update the pinmux configuration based on the actual use case, we should also clean up these forces.

Contributor guide

Open the contributing guide

Research direction

Start with the chip-level sysrst test and PR 13216 to understand where the pad IO are forced in the vseq. Review the pinmux configuration for the actual use case, then remove the obsolete forces once that configuration is updated and verify the sysrst test still works.

Written by the indexing model from the issue text.

Assessment

Domain
testing-qa
Issue type
Refactor
Difficulty
4/5
Estimated time
3-5 days
Activity status
Stale
Clarity
Needs clarification
Newbie friendliness
25/100

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