[opentitantool] Misleading error message when UARTs are not found
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- SystemVerilog
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Description
As an example, if I pass in `--cw310-uarts=/dev/` when running an FPGA test, I will see this in the log:
```
...
[2022-06-06T20:48:26Z INFO opentitantool::command::load_bitstream] Loading bitstream: "external/bit
streams/cache/0124ced9192e6aa2e7f5049164626fb56555ad18/lowrisc_systems_chip_earlgrey_cw310_0.1.bit.o
rig"
[2022-06-06T20:48:26Z INFO opentitanlib::util::rom_detect] Bitstream USR_ACCESS value: 0x2b2c87c8
Error: Opening: No such file or directory
...
```
While reading through the stacktrace below it will reveal that it's having trouble opening the UART, the error message is misleading and suggests that it's having trouble finding the bitstream.
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