[dv/tooling] Improve publish results script
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Component:Tooling
Earlgrey-PROD Triaged
Priority:P3
- Dominant language
- SystemVerilog
- Stars
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- Avg merge
- 2d 22h
- Merged PRs (30d)
- 141
Description
Currently for DV regression, Dvsim won't publish results until all IPs/chip level tests finish running. If one IP gets stuck, we won't be able to publish the results.
A better way would be to publish the results immediately once a IP/chip finished running.
FYI @rswarbrick @weicaiyang
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by locating the Dvsim publish-results script and the DV regression flow that waits for all IP and chip-level tests. Confirm how completion is detected for each IP or chip, then verify that results are published as each one finishes even when another remains stuck.
Written by the indexing model from the issue text.
Assessment
- Domain
- testing-qa, tooling
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 35/100