[fpga] Pinout alignments for integration testing

In order to facilitate debug and integration testing, we need to make sure both the FPGA and ASIC mappings are aligned. Specifically, that means the pinmux should be configured to map out all relevant interfaces as defined by the main use case, and the ASIC testbench and FPGA XDC files need to be aligned accordingly.

While this is possible for most functional IOs, it is a bit more complicated with IOs that have additional DFT functionality multiplexed on top. Specifically, the SPI and JTAG pins are currently multiplexed and connected to SAM3X at the moment. This is due to historical reasons mostly, since on a previous board both interfaces had to share one FTDI connection. On the ASIC the JTAG pins are muxed onto regular GPIOs instead, and we need to align that to enable integration testing. This should be possible with the SAM3X by emulating one of the interfaces using SAM3X GPIOs (see @a-will's comment https://github.com/lowRISC/opentitan/pull/12633#discussion_r872044580).

So overall the tasks can roughly be grouped as follows:

• Update pinmux mapping and configure all functional interfaces used in the primary use case.
• Figure out how to disentangle the SPI and JTAG going to SAM3X on the FPGA boards.
• Create a second XDC and FPGA build target for CW310 that reuses the same RTL sources. This will be used for integration testing where most pins are being routed to user headers on the board.
• Align ASIC testbench and connect corresponding agents accordingly. This requires additional muxing support on the TB side for interfaces that are multiplexed with DFT features.
• Align Verilator testbench. We will likely run a subset of chip-level tests there, hence testbench may not need the same level of TB muxing support as the ASIC testbench. See also #6103.

Start with the Verilator testbench and the related context in #6103. Determine the subset of chip-level tests it must support and align the testbench mappings accordingly; done when those integration tests run with the FPGA and ASIC pinout expectations.