[dv/exclusions] Change handling of full-chip exclusions
Open
@jdonjdon is already working on this.
Since Apr 13, 2023.
Component:DV
IP:clkmgr
IP:pwrmgr
IP:rstmgr
Priority:P3
- Dominant language
- SystemVerilog
- Stars
- 3.6k
- Forks
- 1.1k
- Avg merge
- 2d 22h
- Merged PRs (30d)
- 141
Description
In clkmgr, rstmgr, and pwrmgr the CSR exclusions for full-chip are coded in the hjson file. This means by default
they are not tested in IPs. A better way to deal is to remove these exclusions and explicitly add them in the full chip
base sequence. That way we would err on the side of caution.
> estimate 4
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Assessment
This issue has not been assessed yet.