[clkmgr, fpga] Enhance clkmgr to allow for different types of clock gates per module
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Component:FPGA
Earlgrey-PROD Triaged
IP:clkmgr
Priority:P2
TOP:earlgrey
Type:FutureRelease
- Dominant language
- SystemVerilog
- Stars
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- Forks
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- Avg merge
- 2d 22h
- Merged PRs (30d)
- 141
Description
Specifically, allow additional attributes in the top hjson file to specify what kind of FPGA clock gates a particular module should use.
See #11063 for motivation.
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by reading the clkmgr implementation and the top HJSON configuration, then review issue #11063 for the motivation. The change should let each module specify its FPGA clock-gate type through additional top-level HJSON attributes; no specific files or tests are named.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 35/100