lowRISC / lowRISC/opentitan

[ast / clkmgr] Absorb clock dividers directly into ast

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#11,037 3 comments 0 reactions 5 assignees View on GitHub

@jeoongp is already working on this.

Since Apr 14, 2022.

Component:RTL Earlgrey-PROD Triaged IP:ast IP:clkmgr Priority:P3 Type:FutureRelease
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SystemVerilog
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Description

This is a long term enhancement.
We should ideally absorb the `clkmgr` clock dividers directly into `AST` in the long term.
This resolves a lot of corner cases around how clock bypass is handled, and also makes it easier to control when dividers are stepped down based on such a bypass.

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